RISC-V

RISC-V CPU Core in VHDL

Copyright (C) 2025 4137314

This file is part of the RISC-V CPU project.

This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program. If not, see https://www.gnu.org/licenses/.

Overview

This project implements a RISC-V CPU core in VHDL suitable for FPGA prototyping and educational purposes. The design currently supports the RV32I base integer instruction set, with modular architecture that allows easy extension to RV32IM (multiply/divide), pipeline stages, and peripheral interfaces.

Features

• Two interchangeable RV32IM+Zicsr cores behind one top level (PIPELINED generic):
  • core_single — single-cycle datapath (1 CPI for RV32I ops)
  • core_pipeline — classic 5-stage pipeline (IF/ID/EX/MEM/WB) with forwarding, load-use hazard stall and branch resolution in EX
• Full RV32I: ALU ops, branches, JAL/JALR, LB/LH/LW/LBU/LHU, SB/SH/SW, LUI/AUIPC, FENCE-as-NOP
• Modular ISA extensions, each behind its own generic (RISC-V style):
  • ENABLE_M — full RV32M via a sequential mul/div unit (2-cycle multiply, ~35-cycle restoring divider, spec-compliant div-by-zero/overflow)
  • ENABLE_ZICSR — machine CSRs (mstatus/misa/mie/mip/mtvec/mscratch/mepc/ mcause/mhartid/mcycle(h)/minstret(h)), CSRR* instructions, ECALL/EBREAK/ illegal traps to mtvec, MRET, WFI-as-NOP and machine interrupts (software, timer, external) with cancel-and-reexecute semantics
• SoC top level with a decoded data bus:
  • 0x0000_0000 data RAM - 0x0200_0000 CLINT (msip, mtimecmp, mtime)
  • 0x1000_0000 UART (8N1 TX+RX, polled status), wired to the board’s USB-serial bridge in board_top.xdc
• Modular design: control unit, ALU, register file, PC, immediate generator, branch unit, hazard/forwarding units, record-based pipeline registers
• Verified against the official riscv-arch-test suites (rv32i_m/I and rv32i_m/M, old framework with golden reference signatures) on both cores: sw/arch_test/run_arch_tests.sh — plus a self-checking directed suite (88 tests, sw/gen_tests.py) covering RV32IM, Zicsr, timer/software interrupt round-trips and UART TX/RX loopback; both cores also verified to produce identical memory signatures (hw/scripts/ci_compliance.sh)
• Reproducible dev environment (flake.nix + flake.lock): GHDL, GTKWave, riscv32-none-elf GCC, LaTeX
• Synthesizable with GHDL (--synth) and Vivado (hw/scripts/synthesis.tcl)

Usage

1. Simulation (GHDL):
   • make hw — compile everything and run the default testbench (tb_riscv_core).
   • make hw TB=tb_alu — run a specific testbench (tb_alu, tb_regfile, …).
   • make wave TB=tb_alu — open the resulting waveform in GTKWave.
2. Synthesis:
   • make synth-check — fast synthesizability check with ghdl --synth (no Vivado needed).
   • make synth [PART=xc7a35tcpg236-1] [TOP=riscv] — full Vivado batch flow (hw/scripts/synthesis.tcl): synthesis, place & route, bitstream in hw/build/vivado/.
   • Pin/timing constraints live in hw/constraints/board_top.xdc (Basys3 defaults).
3. Program Loading:
   • The instruction memory is initialized from a hex file (one 32-bit word per line); the default image is sw/program.hex (source in sw/program.S).
   • Compile RISC-V assembly or C programs with a riscv32 toolchain and convert them with objcopy -O verilog --verilog-data-width=4.

Extensions

• Implement a full 5-stage pipeline with hazard detection and forwarding
• Add Multiply/Divide instructions (RV32M)
• Add compressed instructions (RV32C)
• Add floating-point unit (RV32F/D)
• Connect peripherals through AXI4/Wishbone bus
• Integrate accelerators (e.g., TPU or DSP)

References

• RISC-V Instruction Set Manual: https://riscv.org/technical/specifications/
• IEEE 1076-2019 VHDL Standard: https://standards.ieee.org/standard/1076-2019.html
• FPGA vendor documentation (Xilinx, Intel, Lattice)

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